Semiconductor chip or integrated circuit device packages are conventionally manufactured using encapsulating processes so as to minimize physical damage to the chips and the somewhat fragile interconnecting circuitry so that the resulting modules can readily be used, for example, as components mounted on a circuit board on which the components are connected by external contacts or leads provided by the modules. The encapsulation results in preventing physical damage to the sensitive elements of the package. The encapsulation also acts as a corrosion preventative to prevent moisture from reaching and thereby damaging the various sensitive aspects of the package. Transfer molding process techniques are well suited to produce encapsulation for certain types of semiconductor chip packages.
In the integrated circuit module manufacturing industry, there are generally three conventional package arrangement types referred to as leadframe, chip-up laminate and cavity laminate package. In the manufacture of the first two of these types of packages, the processes have become substantially automated whereas the cavity package module does not readily lend itself to encapsulation by the use of presently known techniques for automated transfer molding encapsulation. In standard automated transfer molding processes for leadframe or chip-up laminate packages, the encapsulant covers the entire module or at least an entire surface of the module. This is achievable because of the relatively easy access in the molds used in the transfer molding process to the portion of the module to be encapsulated. With respect to a cavity package, however, it may be difficult to reach the part of the module to be encapsulated with the molten plastic in a transfer molding process, as the channel or runner cannot be designed in the normal way without possible damage to the pin grid array or ball grid array. Various patents and encapsulation arrangements will now be presented which further describe these generalized known characterizations.
U.S. Pat. No. 5,275,546 which issued on Jan. 4, 1994, and U.S. Pat. No. 5,326,243 which issued on Jul. 5, 1994, both to Richard h. J. Fierkens, are examples of known apparatus and processes for encapsulating semiconductor chips in plastic which are mounted on leadframes and which employ transfer molding techniques. Each of these patents describe apparatus having a lower and upper mold defining a cavity in which is positioned a leadframe on which an integrated circuit chip is bonded. Liquid plastic is forced into a cavity formed by the molds, resulting in the chip and the portions of the leadframe adjacent thereto to be completely enclosed within the plastic material. The resultant module package has leads extending therefrom that can then be used to connect the package to other circuitry or to mount on a circuit board. This process and apparatus are adaptable molding automation processes.
As another example of a process for encapsulating semiconductor devices, U.S. Pat. No. 5,182,853 which issued to Kobayashi et al on Feb. 2, 1993, and assigned to Fujitsu Limited, teaches encapsulating a structure of a chip or die referred to as "die-up ball grid array package" or "chip-on-board package". As can be seen from the teachings of this patent, and as is typical of known cavity packages, the encapsulating method used is a globe top process as opposed to transfer molding process, and the entire surface structure is encapsulated, right out to the extremities of the substrate. The complete encapsulation exists on one side of the module.
Another known contact grid array package configuration includes a chip mounted on one side of a substrate or carrier, and a connecting contact grid array on the opposite side of the substrate from the array. The chip and the array are electrically interconnected as is known. This provides a relatively straightforward arrangement for using convention automated encapsulating processes as the liquid encapsulant can be readily brought to the surface of the substrate on which the chip is positioned to be encapsulated.
U.S. Pat. No. 4,688,152 which issued to C. J. Chia on Aug. 18, 1987, and assigned to National Semiconductor Corporation, provides an example of a molded pin grid package in which the pins and the integrated circuit device are located on opposite sides of a substrate. The teachings of this patent describe a relatively straightforward process of encapsulating such a device such that the pin grid array is left uncoated so that the pins can be connected to a circuit board, for example, in second level assembly.
U.S. Pat. No. 4,868,349 which also issued to C. J. Chia on Sept. 19, 1989, and assigned to National Semiconductor Corporation, provides for an improvement of the pin grid package of the previously mentioned patent reference. This patent describes a somewhat conventional transfer molding operation for encapsulating a pin grid array semiconductor package, resulting in a molded device. The teachings of this particular patent result in fluid plastic being formed on both sides of the module such that fluid plastic from the feed runner passes through a series of holes in the carrier to thereby provide a continuous encapsulation on both sides of the module.
U.S. Pat. No. 5,519,936, issued to F. Andros on May 28, 1996 and assigned to International Business Machines Corporation, defines a ball grid array (BGA) package which utilizes a flexible circuitized substrate as part thereof The package's chip is on the same side of the heat sink (31) as the substrate and solder ball connections.
All of the above patents are incorporated herein by reference.